The process of manufacturing an integrated circuit or, more specifically, an application specific integrated circuit (chip) can be very complex. It may involve many processing steps, such as depositing a plurality of similar and/or dissimilar thin-film layers, etching, polishing and/or material removing similar and/or dissimilar thin-film layers, and implanting ions or dopants into various regions of a substrate and/or thin film layers, among many others steps. The process of manufacturing chips may be further complicated if distinct circuits and/or structures are formed on the same integrated circuit substrate. Often these distinct circuits and/or structures have different thin-film layer requirements, which leads them to have different thickness. Thus, forming them on a single substrate can create an irregular or uneven top surface topology.
Because of the resulting irregular or uneven top surface topology when generally distinct circuits and/or structures are formed on an integrated circuit substrate, a layer of material deposited on top of the surface substantially mimics the irregularity or unevenness of the underlying top surface topology. Such layer of material deposited on top of circuits and/or structures may include, for example, a dielectric layer, for separating and/or isolating the underlying circuits and/or structures from other circuits and/or structures such as an inter-layer dielectric (ILD) or an inter-metal-dielectric (IMD). It is essential that the dielectric layer have a substantially even top surface topology so that the overlying circuits and/or structures are formed on a surface having a substantially uniform height. Accordingly, planarization of the dielectric layer is typically undertaken.
FIG. 1 illustrates a cross-sectional view of a chip 10 having an embedded dynamic read access memory (DRAM) structure 12 formed at one region of the chip 10, and having an application-specific integrated circuit (ASIC) or periphery 14 of the chip 10. The DRAM structure 12 typically includes an electrically conductive layer, such as metallic conductors 16. As a result, it generally causes the embedded DRAM structure 12 to have a thickness requirement that is greater than other circuits, structures or regions of the chip 10, such as the ASIC region 14 of the chip 10. As a result, an ILD or IMD layer 18 uniformly deposited on top of both the embedded DRAM structure 12 and the ASIC region 14 of the chip 10 has an uneven top surface topology. This may result in the top surface of the ILD or IMD dielectric layer 18 having a height differential of .DELTA.H from region-to-region of the chip 10. In order to substantially level the top surface of the ILD or IMD dielectric layer 18, conventional prior art planarization processes, such as involving sacrificial oxide etch back or chemical-mechanical polishing (CMP) without dummy pattern, are undertaken. These conventional prior art planarization processes, however, typically have undesirable side effects, such as they cannot reach global planarization. Hence, substantially interfering subsequent manufacturing processes.
FIGS. 2A-2C illustrate cross-sectional views of a chip 20 at sequential steps of a conventional prior art planarization process. As shown in FIG. 2A, the chip 20 used in this example has an embedded DRAM structure 22 formed at one region of the chip 20, and at another region such as ASIC or periphery 24 of the chip 20. For this example, it is assumed that the embedded DRAM structure 22 has a greater thickness than that of the ASIC region 24 of the chip 20. Accordingly, a dielectric layer 26 uniformly deposited on top of the embedded DRAM structure 22 and the ASIC region 24 of the chip 20 has an irregular or uneven top surface topology due to the difference in the thickness of the regions 22 and 24. This example chip 20 as described is the starting point for the conventional prior art planarization process described below with reference to FIGS. 2A-2C.
As illustrated in FIG. 2A, the conventional prior art planarization process begins by forming a layer of photoresist 28 on top of the dielectric layer 26 substantially above the ASIC region 24 of the chip 20, i.e., the region having a lower thickness requirement. The photoresist layer 28 may overlie a portion of a region of the dielectric layer 26 that is situated between the embedded DRAM structure 22 and the region 24 of the chip 20. However, no photoresist is formed on top of the dielectric layer 26 at the region directly over the embedded DRAM structure 22 and the remaining portion of the region between regions 22 and 24, so as to leave these regions exposed.
As illustrated in FIG. 2B, a second step in the conventional prior art planarization process is to perform an etching of the dielectric layer 26 at the regions not being masked by the photoresist 28, i.e. the region of the dielectric layer 26 that substantially overlies the embedded DRAM structure 22 (outlined in FIG. 2B as a dashed line since the material in that region has been removed). The etching of the dielectric layer 26 is performed in a manner that the height of the dielectric layer 26 overlying the embedded DRAM structure 22 is substantially the same height of the dielectric layer 26 overlying the ASIC region 24 of the chip 20. The photoresist 28 protects or masks the dielectric layer 26 overlying the region 24 from the etching step. As a result, at the completion of this step, the ILD or IMD layer 26 is somewhat planarized, except for a raised region 30 situated between the embedded DRAM structure 22 and the ASIC region 24 of the chip 20. The photoresist 28 is subsequently removed.
As illustrated in FIG. 2C, a final step in the conventional prior art planarization process is to perform a chemical-mechanical polishing (CMP) of the dielectric layer 26. This CMP step removes the raised region 30 and substantially planarizes the dielectric layer 26. The disadvantage of this conventional prior art planarization process is that it requires a photolithography step as described above with reference to FIG. 2A. This photolithography step is not desired since it increases the manufacturing time of the chip 20, increases the cost of producing the chip 20, and increases the complexity of the planarization process. Thus, there is a need for a method of planarizing the dielectric layer 26, or any irregular or uneven surface, without having to perform a photolithography step.
FIGS. 3A-3E illustrate cross-sectional views of an irregular or uneven top surface of a layer of material, such as a dielectric layer 50, at sequential steps of a second conventional prior art planarization process. For example, in the planarization of a shallow trench isolation (STI) process, a polysilicon layer is utilized as a self-aligned mask. As illustrated in FIG. 3A, the top surface of the dielectric layer 50 has an irregular or uneven topology, including alternating upper portions 52a and alternating lower portions 54a . FIG. 3A also illustrates the dielectric layer 50 at the start of the second conventional prior art planarization process.
As illustrated in FIG. 3B, a first step in the second conventional prior art planarization process is to deposit a conformal layer of a sacrificial oxide 56 over the uneven top surface of the dielectric layer 50, and deposit a conformal layer of polysilicon 58 over the sacrificial oxide layer 56. The polysilicon layer 58 is deposited using low pressure chemical vapor deposition (LPCVD) at a temperature of about 700 degrees Celsius. Since the top surface of the dielectric layer 50 has alternating upper portions 52a and alternating lower portions 54a, the sacrificial oxide layer 56 and the polysilicon layer 58 also have corresponding upper portions 52b and 52c, and corresponding lower portions 54b and 54c, respectively.
As illustrated in FIG. 3C, a second step in the second conventional prior art planarization process is to perform a first chemical-mechanical polishing (CMP) of the polysilicon layer 58 in order to remove the upper portions 52c of the polysilicon layer 58. This step leaves behind the lower portions 54c of the polysilicon layer 58, which serve as self-aligned masks for a subsequent etching step. This step also leaves the top surface of the upper portions 52b of the sacrificial oxide layer 56 exposed.
As illustrated in FIG. 3D, a third step in the second conventional prior art planarization process is to perform an etching of the upper portions 52b of the sacrificial oxide layer 56. The remaining lower portions 54c of the polysilicon layer 58 serve as self-aligned masks that help in defining the upper portions 52b of the sacrificial oxide layer 56. As a result, a plurality of channels 60 are formed within the sacrificial oxide layer 56 that are each at substantially the same height.
As illustrated in FIG. 3E, a final step in the second conventional prior art planarization process is to perform a second chemical-mechanical polishing (CMP) step to remove the remaining lower portions 54b and 54c of the sacrificial oxide layer 56 and the polysilicon layer 58, respectively, and to substantially planarize the top surface of the dielectric layer 50. The disadvantage with the second conventional prior art planarization process is that it requires the deposition of the polysilicon layer 58 using LPCVD at a relatively high temperature, i.e. at a temperature about 700 degrees Celsius. Such a high temperature has substantial adverse effects on metal conductors present in a chip, which results in a planarization process that is substantially not feasible. Accordingly, there is a need for a method of planarizing the dielectric layer 50, or any irregular or uneven surface, without having to perform any step which subjects the chip to such a high temperature.